Novel flexible buffering architectures for 3D-NoCs

In the conventional router architecture of Network-on-Chips (NoCs), each input port employs a set dedicated flit buffers to store incoming flits. This mechanism unevenly distributes flits among buffers, which in turn leads higher packet blocking rates and under-utilization buffers. this paper, we address problem by proposing two novel buffering mechanisms their corresponding architectures share several ports efficiently. Our first proposed is called Minimum-First buffering. based on number free buffer slots available port, giving priority minimum occupied approach increases utilization underutilized allowing them other ports. The second (so-called Inverse-Priority buffering) lighter yet efficient, flexible technique. simple order for buffer. According our analysis, prioritizing specific over others balances traffic loads between thus yields throughput. Both lead lower waiting times hardware resources. After studying all possible scenarios analyzing corner cases, have optimally designed equipped with mechanisms. Moreover, optimization technique introduced reduce area overhead architecture. show significant improvements performance 3D-NoCs terms average network throughput delay as well total blocked packets compared different state-of-the-art baseline architectures.